Beschreibung
InhaltsangabeForeword. Preface. 0. Giving Semantics to VHDL: an Introduction; C. Delgado Kloos, P.T. Breuer. 1. A Functional Semantics for Delta-Delay VHDL Based on Focus; M. Fuchs, M. Mendler. 2. A Functional Semantics for Unit-Delay VHDL; P.T. Breuer, L. Sánchez Fernanández, C. Delgado Kloos. 3. An Operational Semantics for a Subset of VHDL; J.P. Van Tassel. 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines; E. Börger, U. Glässer, W. Müller. 5. A Formal Model of VHDL Using Coloured Petri Nets; S. Olcoz. 6. A Deterministic Finite-State Model for VHDL; G. Döhmen, R. Herrmann. 7. A Flow Graph Semantics of VHDL: a Basis for Hardware Verification with VHDL; R. Reetz, T. Kropf. References.
Produktsicherheitsverordnung
Hersteller:
Springer Verlag GmbH
juergen.hartmann@springer.com
Tiergartenstr. 17
DE 69121 Heidelberg
Autorenportrait
InhaltsangabeForeword. Preface. 0. Giving Semantics to VHDL: an Introduction; C. Delgado Kloos, P.T. Breuer. 1. A Functional Semantics for Delta-Delay VHDL Based on Focus; M. Fuchs, M. Mendler. 2. A Functional Semantics for Unit-Delay VHDL; P.T. Breuer, L. Sánchez Fernanández, C. Delgado Kloos. 3. An Operational Semantics for a Subset of VHDL; J.P. Van Tassel. 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines; E. Börger, U. Glässer, W. Müller. 5. A Formal Model of VHDL Using Coloured Petri Nets; S. Olcoz. 6. A Deterministic Finite-State Model for VHDL; G. Döhmen, R. Herrmann. 7. A Flow Graph Semantics of VHDL: a Basis for Hardware Verification with VHDL; R. Reetz, T. Kropf. References.
